ATmega32A - I2CRAM – TWI - Sequential Read

Quote from KerimF on September 11, 2025, 10:03 amHi,
SimulIDE_1.1.0-R250812_Win32, W7
ATmega32A, I2CRAM , TWI
In Master Receiver Mode, ‘SLA+R‘ is sent to start a sequential read from I2CRAM. Then, two bits in TWCR are set; TWEN (to enable the 2-wire Serial Interface) and TWINT (to clear it). The MCU (ATmega32A) receives the addressed byte from I2CRAM, but without Acknowledge (though a returned Acknowledge is expected, to continue the read transfer).
Therefore, sending again TWEN and TWINT, the bit TWINT won’t be set again as usual, and the read transfer is halted.
For instance, to signal I2CRAM that the last byte will be read; only TWINT is sent (no returned Acknowledge is expected).
But perhaps I missed something.
My workaround is by resending the ‘Repeated START’ followed by ‘SLA+R‘, in order to read the next byte, and so on.
Thank you.
Hi,
SimulIDE_1.1.0-R250812_Win32, W7
ATmega32A, I2CRAM , TWI
In Master Receiver Mode, ‘SLA+R‘ is sent to start a sequential read from I2CRAM. Then, two bits in TWCR are set; TWEN (to enable the 2-wire Serial Interface) and TWINT (to clear it). The MCU (ATmega32A) receives the addressed byte from I2CRAM, but without Acknowledge (though a returned Acknowledge is expected, to continue the read transfer).
Therefore, sending again TWEN and TWINT, the bit TWINT won’t be set again as usual, and the read transfer is halted.
For instance, to signal I2CRAM that the last byte will be read; only TWINT is sent (no returned Acknowledge is expected).
But perhaps I missed something.
My workaround is by resending the ‘Repeated START’ followed by ‘SLA+R‘, in order to read the next byte, and so on.
Thank you.

Quote from arcachofo on September 15, 2025, 10:24 amHi.
The MCU (ATmega32A) receives the addressed byte from I2CRAM, but without Acknowledge (though a returned Acknowledge is expected, to continue the read transfer).
Not sure if I understand what you mean, but isn't the Master who should ACK the byte received?
As I understand the sequential read, the Slave sends a byte and it keeps sending while it receives an ACK from the Master.
To stop the sequential read, the Master sends a NACK and Stop.
Hi.
The MCU (ATmega32A) receives the addressed byte from I2CRAM, but without Acknowledge (though a returned Acknowledge is expected, to continue the read transfer).
Not sure if I understand what you mean, but isn't the Master who should ACK the byte received?
As I understand the sequential read, the Slave sends a byte and it keeps sending while it receives an ACK from the Master.
To stop the sequential read, the Master sends a NACK and Stop.

Quote from KerimF on September 15, 2025, 5:14 pmQuote from arcachofo on September 15, 2025, 10:24 amHi.
The MCU (ATmega32A) receives the addressed byte from I2CRAM, but without Acknowledge (though a returned Acknowledge is expected, to continue the read transfer).
Not sure if I understand what you mean, but isn't the Master who should ACK the byte received?
As I understand the sequential read, the Slave sends a byte and it keeps sending while it receives an ACK from the Master.
To stop the sequential read, the Master sends a NACK and Stop.Hi,
You are right.
Now the question is:
How we let the MCU receive a byte and respond by ACK.
To my knowledge, first we load TWDR with SLA_R. Then, we set two bits in TWCR; TWEN and TWINT.
And after the MCU receives a byte, it is supposed to respond with ACK (otherwise, which bits in TWCR need to be set first?)
And as long TWEN and TWINT are set after every received byte, more bytes will be received till... TWINT only is set.
But perhaps I missed something else.
Quote from arcachofo on September 15, 2025, 10:24 amHi.
The MCU (ATmega32A) receives the addressed byte from I2CRAM, but without Acknowledge (though a returned Acknowledge is expected, to continue the read transfer).
Not sure if I understand what you mean, but isn't the Master who should ACK the byte received?
As I understand the sequential read, the Slave sends a byte and it keeps sending while it receives an ACK from the Master.
To stop the sequential read, the Master sends a NACK and Stop.
Hi,
You are right.
Now the question is:
How we let the MCU receive a byte and respond by ACK.
To my knowledge, first we load TWDR with SLA_R. Then, we set two bits in TWCR; TWEN and TWINT.
And after the MCU receives a byte, it is supposed to respond with ACK (otherwise, which bits in TWCR need to be set first?)
And as long TWEN and TWINT are set after every received byte, more bytes will be received till... TWINT only is set.
But perhaps I missed something else.

Quote from arcachofo on September 15, 2025, 7:16 pmI think the key is in bit TWCR:TWEA, set to 1 to generate ACK when receiving a byte, set to 0 to generate NACK and stop sequential reading.
I think the key is in bit TWCR:TWEA, set to 1 to generate ACK when receiving a byte, set to 0 to generate NACK and stop sequential reading.

Quote from KerimF on September 16, 2025, 6:04 amQuote from arcachofo on September 15, 2025, 7:16 pmI think the key is in bit TWCR:TWEA, set to 1 to generate ACK when receiving a byte, set to 0 to generate NACK and stop sequential reading.
You are totally right, as usual. I knew I was missing something 🙁
On the datasheet of ATmega32A, the word 'TWEA' is split on two lines, TWE and A (below TWE), on the 'Table 24-4 Status codes for Master Receiver Mode' (page 239). Whenever I revised the table, my brain assumed always that the missing 4th letter is N (that is TWEN) though the letter A is printed clearly below TWE.
Thank you for your help.
Quote from arcachofo on September 15, 2025, 7:16 pmI think the key is in bit TWCR:TWEA, set to 1 to generate ACK when receiving a byte, set to 0 to generate NACK and stop sequential reading.
You are totally right, as usual. I knew I was missing something 🙁
On the datasheet of ATmega32A, the word 'TWEA' is split on two lines, TWE and A (below TWE), on the 'Table 24-4 Status codes for Master Receiver Mode' (page 239). Whenever I revised the table, my brain assumed always that the missing 4th letter is N (that is TWEN) though the letter A is printed clearly below TWE.
Thank you for your help.