#pragma once

#include "hw/hw.h"
#include "hw/sysbus.h"
#include "hw/registerfields.h"

#include "hw/misc/esp32c3_reg.h"

#define TYPE_ESP32C3_RTC_CNTL "misc.esp32c3.rtc_cntl"
#define ESP32C3_RTC_CNTL(obj) OBJECT_CHECK(ESP32C3RtcCntlState, (obj), TYPE_ESP32C3_RTC_CNTL)

#define BIT_SET(reg, bit)   ((reg) & BIT(bit))
#define CLEAR_BIT(reg, bit) do { (reg) &= ~BIT(bit); } while(0)
#define SET_BIT(reg, bit)   do { (reg) |= BIT(bit); } while(0)

#define ESP32C3_RTC_CPU_RESET_GPIO    "cpu-reset"

/**
 * Size of the I/O space for the RTC CTNL.
 */
#define ESP32C3_RTC_CNTL_IO_SIZE    (A_RTC_CNTL_DATE + 4)

typedef enum ESP32C3ResetReason {
    ESP32C3_NO_MEAN                =  0,
    ESP32C3_POWERON_RESET          =  1,    /**<1, Vbat power on reset*/
    ESP32C3_RTC_SW_SYS_RESET       =  3,    /**<3, Software reset digital core*/
    ESP32C3_DEEPSLEEP_RESET        =  5,    /**<5, Deep Sleep reset digital core*/
    ESP32C3_TG0WDT_SYS_RESET       =  7,    /**<7, Timer Group0 Watch dog reset digital core*/
    ESP32C3_TG1WDT_SYS_RESET       =  8,    /**<8, Timer Group1 Watch dog reset digital core*/
    ESP32C3_RTCWDT_SYS_RESET       =  9,    /**<9, RTC Watch dog Reset digital core*/
    ESP32C3_INTRUSION_RESET        = 10,    /**<10, Instrusion tested to reset CPU*/
    ESP32C3_TG0WDT_CPU_RESET       = 11,    /**<11, Time Group0 reset CPU*/
    ESP32C3_RTC_SW_CPU_RESET       = 12,    /**<12, Software reset CPU*/
    ESP32C3_RTCWDT_CPU_RESET       = 13,    /**<13, RTC Watch dog Reset CPU*/
    ESP32C3_RTCWDT_BROWN_OUT_RESET = 15,    /**<15, Reset when the vdd voltage is not stable*/
    ESP32C3_RTCWDT_RTC_RESET       = 16,    /**<16, RTC Watch dog reset digital core and rtc module*/
    ESP32C3_TG1WDT_CPU_RESET       = 17,    /**<17, Time Group1 reset CPU*/
    ESP32C3_SUPER_WDT_RESET        = 18,    /**<18, super watchdog reset digital core and rtc module*/
    ESP32C3_GLITCH_RTC_RESET       = 19,    /**<19, glitch reset digital core and rtc module*/
    ESP32C3_EFUSE_RESET            = 20,    /**<20, efuse reset digital core*/
    ESP32C3_USB_UART_CHIP_RESET    = 21,    /**<21, usb uart reset digital core and rtc module */
    ESP32C3_USB_JTAG_CHIP_RESET    = 22,    /**<22, usb jtag reset digital core and rtc module*/
    ESP32C3_POWER_GLITCH_RESET     = 23,    /**<23, power glitch reset digital core and rtc module*/
    ESP32C3_COUNT_RESET            = 24
} ESP32C3ResetReason;

#define ESP32C3_RTC_CNTL_SCRATCH_REG_COUNT 8

typedef struct ESP32C3RtcCntlState {
    SysBusDevice parent_obj;
    MemoryRegion iomem;

    uint32_t options0;
    uint32_t scratch_reg[ESP32C3_RTC_CNTL_SCRATCH_REG_COUNT];

    ESP32C3ResetReason reason;
    /* IRQ used to notify the machine that we need a reset */
    qemu_irq cpu_reset;

} ESP32C3RtcCntlState;


REG32(RTC_CNTL_RTC_OPTIONS0, 0x0000)
    FIELD(RTC_CNTL_RTC_OPTIONS0, SW_SYS_RST, 31, 1)
    FIELD(RTC_CNTL_RTC_OPTIONS0, DG_WRAP_FORCE_NORST, 30, 1)
    FIELD(RTC_CNTL_RTC_OPTIONS0, DG_WRAP_FORCE_RST, 29, 1)
    FIELD(RTC_CNTL_RTC_OPTIONS0, XTL_FORCE_PU, 13, 1)
    FIELD(RTC_CNTL_RTC_OPTIONS0, XTL_FORCE_PD, 12, 1)
    FIELD(RTC_CNTL_RTC_OPTIONS0, BBPLL_FORCE_PU, 11, 1)
    FIELD(RTC_CNTL_RTC_OPTIONS0, BBPLL_FORCE_PD, 10, 1)
    FIELD(RTC_CNTL_RTC_OPTIONS0, BBPLL_I2C_FORCE_PU, 9, 1)
    FIELD(RTC_CNTL_RTC_OPTIONS0, BBPLL_I2C_FORCE_PD, 8, 1)
    FIELD(RTC_CNTL_RTC_OPTIONS0, BB_I2C_FORCE_PU, 7, 1)
    FIELD(RTC_CNTL_RTC_OPTIONS0, BB_I2C_FORCE_PD, 6, 1)
    FIELD(RTC_CNTL_RTC_OPTIONS0, SW_PROCPU_RST, 5, 1)
    FIELD(RTC_CNTL_RTC_OPTIONS0, SW_APPCPU_RST, 4, 1)
    FIELD(RTC_CNTL_RTC_OPTIONS0, SW_STALL_PROCPU_C0, 2, 2)

REG32(RTC_CNTL_RTC_SLP_TIMER0, 0x0004)
    FIELD(RTC_CNTL_RTC_SLP_TIMER0, SLP_VAL_LO, 0, 32)

REG32(RTC_CNTL_RTC_SLP_TIMER1, 0x0008)
    FIELD(RTC_CNTL_RTC_SLP_TIMER1, RTC_MAIN_TIMER_ALARM_EN, 16, 1)
    FIELD(RTC_CNTL_RTC_SLP_TIMER1, SLP_VAL_HI, 0, 16)

REG32(RTC_CNTL_RTC_TIME_UPDATE, 0x000C)
    FIELD(RTC_CNTL_RTC_TIME_UPDATE, RTC_TIME_UPDATE, 31, 1)
    FIELD(RTC_CNTL_RTC_TIME_UPDATE, TIMER_SYS_RST, 29, 1)
    FIELD(RTC_CNTL_RTC_TIME_UPDATE, TIMER_XTL_OFF, 28, 1)
    FIELD(RTC_CNTL_RTC_TIME_UPDATE, TIMER_SYS_STALL, 27, 1)

REG32(RTC_CNTL_RTC_TIME_LOW0, 0x0010)
    FIELD(RTC_CNTL_RTC_TIME_LOW0, RTC_TIMER_VALUE0_LOW, 0, 32)

REG32(RTC_CNTL_RTC_TIME_HIGH0, 0x0014)
    FIELD(RTC_CNTL_RTC_TIME_HIGH0, RTC_TIMER_VALUE0_HIGH, 0, 16)

REG32(RTC_CNTL_RTC_STATE0, 0x0018)
    FIELD(RTC_CNTL_RTC_STATE0, SLEEP_EN, 31, 1)
    FIELD(RTC_CNTL_RTC_STATE0, SLP_REJECT, 30, 1)
    FIELD(RTC_CNTL_RTC_STATE0, SLP_WAKEUP, 29, 1)
    FIELD(RTC_CNTL_RTC_STATE0, SDIO_ACTIVE_IND, 28, 1)
    FIELD(RTC_CNTL_RTC_STATE0, APB2RTC_BRIDGE_SEL, 22, 1)
    FIELD(RTC_CNTL_RTC_STATE0, RTC_SLP_REJECT_CAUSE_CLR, 1, 1)
    FIELD(RTC_CNTL_RTC_STATE0, RTC_SW_CPU_INT, 0, 1)

REG32(RTC_CNTL_RTC_TIMER1, 0x001C)
    FIELD(RTC_CNTL_RTC_TIMER1, PLL_BUF_WAIT, 24, 8)
    FIELD(RTC_CNTL_RTC_TIMER1, XTL_BUF_WAIT, 14, 10)
    FIELD(RTC_CNTL_RTC_TIMER1, CK8M_WAIT, 6, 8)
    FIELD(RTC_CNTL_RTC_TIMER1, CPU_STALL_WAIT, 1, 5)
    FIELD(RTC_CNTL_RTC_TIMER1, CPU_STALL_EN, 0, 1)

REG32(RTC_CNTL_RTC_TIMER2, 0x0020)
    FIELD(RTC_CNTL_RTC_TIMER2, MIN_TIME_CK8M_OFF, 24, 8)

REG32(RTC_CNTL_RTC_TIMER3, 0x0024)

REG32(RTC_CNTL_RTC_TIMER4, 0x0028)

REG32(RTC_CNTL_RTC_TIMER5, 0x002C)
    FIELD(RTC_CNTL_RTC_TIMER5, MIN_SLP_VAL, 8, 8)

REG32(RTC_CNTL_RTC_TIMER6, 0x0030)

REG32(RTC_CNTL_RTC_ANA_CONF, 0x0034)
    FIELD(RTC_CNTL_RTC_ANA_CONF, PLL_I2C_PU, 31, 1)
    FIELD(RTC_CNTL_RTC_ANA_CONF, CKGEN_I2C_PU, 30, 1)
    FIELD(RTC_CNTL_RTC_ANA_CONF, RFRX_PBUS_PU, 28, 1)
    FIELD(RTC_CNTL_RTC_ANA_CONF, TXRF_I2C_PU, 27, 1)
    FIELD(RTC_CNTL_RTC_ANA_CONF, PVTMON_PU, 26, 1)
    FIELD(RTC_CNTL_RTC_ANA_CONF, PLLA_FORCE_PU, 24, 1)
    FIELD(RTC_CNTL_RTC_ANA_CONF, PLLA_FORCE_PD, 23, 1)
    FIELD(RTC_CNTL_RTC_ANA_CONF, SAR_I2C_PU, 22, 1)
    FIELD(RTC_CNTL_RTC_ANA_CONF, GLITCH_RST_EN, 20, 1)
    FIELD(RTC_CNTL_RTC_ANA_CONF, RESET_POR_FORCE_PU, 19, 1)
    FIELD(RTC_CNTL_RTC_ANA_CONF, RESET_POR_FORCE_PD, 18, 1)

REG32(RTC_CNTL_RTC_RESET_STATE, 0x0038)
    FIELD(RTC_CNTL_RTC_RESET_STATE, RTC_DRESET_MASK_PROCPU, 25, 1)
    FIELD(RTC_CNTL_RTC_RESET_STATE, RTC_DRESET_MASK_APPCPU, 24, 1)
    FIELD(RTC_CNTL_RTC_RESET_STATE, JTAG_RESET_FLAG_CLR_APPCPU, 23, 1)
    FIELD(RTC_CNTL_RTC_RESET_STATE, JTAG_RESET_FLAG_CLR_PROCPU, 22, 1)
    FIELD(RTC_CNTL_RTC_RESET_STATE, JTAG_RESET_FLAG_APPCPU, 21, 1)
    FIELD(RTC_CNTL_RTC_RESET_STATE, JTAG_RESET_FLAG_PROCPU, 20, 1)
    FIELD(RTC_CNTL_RTC_RESET_STATE, OCD_HALT_ON_RESET_PROCPU, 19, 1)
    FIELD(RTC_CNTL_RTC_RESET_STATE, OCD_HALT_ON_RESET_APPCPU, 18, 1)
    FIELD(RTC_CNTL_RTC_RESET_STATE, ALL_RESET_FLAG_CLR_APPCPU, 17, 1)
    FIELD(RTC_CNTL_RTC_RESET_STATE, ALL_RESET_FLAG_CLR_PROCPU, 16, 1)
    FIELD(RTC_CNTL_RTC_RESET_STATE, ALL_RESET_FLAG_APPCPU, 15, 1)
    FIELD(RTC_CNTL_RTC_RESET_STATE, ALL_RESET_FLAG_PROCPU, 14, 1)
    FIELD(RTC_CNTL_RTC_RESET_STATE, STAT_VECTOR_SEL_PROCPU, 13, 1)
    FIELD(RTC_CNTL_RTC_RESET_STATE, STAT_VECTOR_SEL_APPCPU, 12, 1)
    FIELD(RTC_CNTL_RTC_RESET_STATE, RESET_CAUSE_PROCPU, 0, 6)

REG32(RTC_CNTL_RTC_WAKEUP_STATE, 0x003C)
    FIELD(RTC_CNTL_RTC_WAKEUP_STATE, RTC_WAKEUP_ENA, 15, 17)

REG32(RTC_CNTL_INT_ENA_RTC, 0x0040)
    FIELD(RTC_CNTL_INT_ENA_RTC, RTC_BBPLL_CAL_INT_ENA, 20, 1)
    FIELD(RTC_CNTL_INT_ENA_RTC, RTC_GLITCH_DET_INT_ENA, 19, 1)
    FIELD(RTC_CNTL_INT_ENA_RTC, RTC_XTAL32K_DEAD_INT_ENA, 16, 1)
    FIELD(RTC_CNTL_INT_ENA_RTC, RTC_SWD_INT_ENA, 15, 1)
    FIELD(RTC_CNTL_INT_ENA_RTC, RTC_MAIN_TIMER_INT_ENA, 10, 1)
    FIELD(RTC_CNTL_INT_ENA_RTC, RTC_BROWN_OUT_INT_ENA, 9, 1)
    FIELD(RTC_CNTL_INT_ENA_RTC, RTC_WDT_INT_ENA, 3, 1)
    FIELD(RTC_CNTL_INT_ENA_RTC, SLP_REJECT_INT_ENA, 1, 1)
    FIELD(RTC_CNTL_INT_ENA_RTC, SLP_WAKEUP_INT_ENA, 0, 1)

REG32(RTC_CNTL_INT_RAW_RTC, 0x0044)
    FIELD(RTC_CNTL_INT_RAW_RTC, RTC_BBPLL_CAL_INT_RAW, 20, 1)
    FIELD(RTC_CNTL_INT_RAW_RTC, RTC_GLITCH_DET_INT_RAW, 19, 1)
    FIELD(RTC_CNTL_INT_RAW_RTC, RTC_XTAL32K_DEAD_INT_RAW, 16, 1)
    FIELD(RTC_CNTL_INT_RAW_RTC, RTC_SWD_INT_RAW, 15, 1)
    FIELD(RTC_CNTL_INT_RAW_RTC, RTC_MAIN_TIMER_INT_RAW, 10, 1)
    FIELD(RTC_CNTL_INT_RAW_RTC, RTC_BROWN_OUT_INT_RAW, 9, 1)
    FIELD(RTC_CNTL_INT_RAW_RTC, RTC_WDT_INT_RAW, 3, 1)
    FIELD(RTC_CNTL_INT_RAW_RTC, SLP_REJECT_INT_RAW, 1, 1)
    FIELD(RTC_CNTL_INT_RAW_RTC, SLP_WAKEUP_INT_RAW, 0, 1)

REG32(RTC_CNTL_INT_ST_RTC, 0x0048)
    FIELD(RTC_CNTL_INT_ST_RTC, RTC_BBPLL_CAL_INT_ST, 20, 1)
    FIELD(RTC_CNTL_INT_ST_RTC, RTC_GLITCH_DET_INT_ST, 19, 1)
    FIELD(RTC_CNTL_INT_ST_RTC, RTC_XTAL32K_DEAD_INT_ST, 16, 1)
    FIELD(RTC_CNTL_INT_ST_RTC, RTC_SWD_INT_ST, 15, 1)
    FIELD(RTC_CNTL_INT_ST_RTC, RTC_MAIN_TIMER_INT_ST, 10, 1)
    FIELD(RTC_CNTL_INT_ST_RTC, RTC_BROWN_OUT_INT_ST, 9, 1)
    FIELD(RTC_CNTL_INT_ST_RTC, RTC_WDT_INT_ST, 3, 1)
    FIELD(RTC_CNTL_INT_ST_RTC, SLP_REJECT_INT_ST, 1, 1)
    FIELD(RTC_CNTL_INT_ST_RTC, SLP_WAKEUP_INT_ST, 0, 1)

REG32(RTC_CNTL_INT_CLR_RTC, 0x004C)
    FIELD(RTC_CNTL_INT_CLR_RTC, RTC_BBPLL_CAL_INT_CLR, 20, 1)
    FIELD(RTC_CNTL_INT_CLR_RTC, RTC_GLITCH_DET_INT_CLR, 19, 1)
    FIELD(RTC_CNTL_INT_CLR_RTC, RTC_XTAL32K_DEAD_INT_CLR, 16, 1)
    FIELD(RTC_CNTL_INT_CLR_RTC, RTC_SWD_INT_CLR, 15, 1)
    FIELD(RTC_CNTL_INT_CLR_RTC, RTC_MAIN_TIMER_INT_CLR, 10, 1)
    FIELD(RTC_CNTL_INT_CLR_RTC, RTC_BROWN_OUT_INT_CLR, 9, 1)
    FIELD(RTC_CNTL_INT_CLR_RTC, RTC_WDT_INT_CLR, 3, 1)
    FIELD(RTC_CNTL_INT_CLR_RTC, SLP_REJECT_INT_CLR, 1, 1)
    FIELD(RTC_CNTL_INT_CLR_RTC, SLP_WAKEUP_INT_CLR, 0, 1)

REG32(RTC_CNTL_RTC_STORE0, 0x0050)
    FIELD(RTC_CNTL_RTC_STORE0, RTC_SCRATCH0, 0, 32)

REG32(RTC_CNTL_RTC_STORE1, 0x0054)
    FIELD(RTC_CNTL_RTC_STORE1, RTC_SCRATCH1, 0, 32)

REG32(RTC_CNTL_RTC_STORE2, 0x0058)
    FIELD(RTC_CNTL_RTC_STORE2, RTC_SCRATCH2, 0, 32)

REG32(RTC_CNTL_RTC_STORE3, 0x005C)
    FIELD(RTC_CNTL_RTC_STORE3, RTC_SCRATCH3, 0, 32)

REG32(RTC_CNTL_RTC_EXT_XTL_CONF, 0x0060)
    FIELD(RTC_CNTL_RTC_EXT_XTL_CONF, XTL_EXT_CTR_EN, 31, 1)
    FIELD(RTC_CNTL_RTC_EXT_XTL_CONF, XTL_EXT_CTR_LV, 30, 1)
    FIELD(RTC_CNTL_RTC_EXT_XTL_CONF, RTC_XTAL32K_GPIO_SEL, 23, 1)
    FIELD(RTC_CNTL_RTC_EXT_XTL_CONF, RTC_WDT_STATE, 20, 3)
    FIELD(RTC_CNTL_RTC_EXT_XTL_CONF, DAC_XTAL_32K, 17, 3)
    FIELD(RTC_CNTL_RTC_EXT_XTL_CONF, XPD_XTAL_32K, 16, 1)
    FIELD(RTC_CNTL_RTC_EXT_XTL_CONF, DRES_XTAL_32K, 13, 3)
    FIELD(RTC_CNTL_RTC_EXT_XTL_CONF, DGM_XTAL_32K, 10, 3)
    FIELD(RTC_CNTL_RTC_EXT_XTL_CONF, DBUF_XTAL_32K, 9, 1)
    FIELD(RTC_CNTL_RTC_EXT_XTL_CONF, ENCKINIT_XTAL_32K, 8, 1)
    FIELD(RTC_CNTL_RTC_EXT_XTL_CONF, XTAL32K_XPD_FORCE, 7, 1)
    FIELD(RTC_CNTL_RTC_EXT_XTL_CONF, XTAL32K_AUTO_RETURN, 6, 1)
    FIELD(RTC_CNTL_RTC_EXT_XTL_CONF, XTAL32K_AUTO_RESTART, 5, 1)
    FIELD(RTC_CNTL_RTC_EXT_XTL_CONF, XTAL32K_AUTO_BACKUP, 4, 1)
    FIELD(RTC_CNTL_RTC_EXT_XTL_CONF, XTAL32K_EXT_CLK_FO, 3, 1)
    FIELD(RTC_CNTL_RTC_EXT_XTL_CONF, XTAL32K_WDT_RESET, 2, 1)
    FIELD(RTC_CNTL_RTC_EXT_XTL_CONF, XTAL32K_WDT_CLK_FO, 1, 1)
    FIELD(RTC_CNTL_RTC_EXT_XTL_CONF, XTAL32K_WDT_EN, 0, 1)

REG32(RTC_CNTL_RTC_EXT_WAKEUP_CONF, 0x0064)
    FIELD(RTC_CNTL_RTC_EXT_WAKEUP_CONF, GPIO_WAKEUP_FILTER, 31, 1)

REG32(RTC_CNTL_RTC_SLP_REJECT_CONF, 0x0068)
    FIELD(RTC_CNTL_RTC_SLP_REJECT_CONF, DEEP_SLP_REJECT_EN, 31, 1)
    FIELD(RTC_CNTL_RTC_SLP_REJECT_CONF, LIGHT_SLP_REJECT_EN, 30, 1)
    FIELD(RTC_CNTL_RTC_SLP_REJECT_CONF, RTC_SLEEP_REJECT_ENA, 12, 17)

REG32(RTC_CNTL_RTC_CPU_PERIOD_CONF, 0x006C)
    FIELD(RTC_CNTL_RTC_CPU_PERIOD_CONF, RTC_CPUPERIOD_SEL, 30, 2)
    FIELD(RTC_CNTL_RTC_CPU_PERIOD_CONF, RTC_CPUSEL_CONF, 29, 1)

REG32(RTC_CNTL_RTC_CLK_CONF, 0x0070)
    FIELD(RTC_CNTL_RTC_CLK_CONF, ANA_CLK_RTC_SEL, 30, 2)
    FIELD(RTC_CNTL_RTC_CLK_CONF, FAST_CLK_RTC_SEL, 29, 1)
    FIELD(RTC_CNTL_RTC_CLK_CONF, XTAL_GLOBAL_FORCE_NOGATING, 28, 1)
    FIELD(RTC_CNTL_RTC_CLK_CONF, XTAL_GLOBAL_FORCE_GATING, 27, 1)
    FIELD(RTC_CNTL_RTC_CLK_CONF, CK8M_FORCE_PU, 26, 1)
    FIELD(RTC_CNTL_RTC_CLK_CONF, CK8M_FORCE_PD, 25, 1)
    FIELD(RTC_CNTL_RTC_CLK_CONF, CK8M_DFREQ, 17, 8)
    FIELD(RTC_CNTL_RTC_CLK_CONF, CK8M_FORCE_NOGATING, 16, 1)
    FIELD(RTC_CNTL_RTC_CLK_CONF, XTAL_FORCE_NOGATING, 15, 1)
    FIELD(RTC_CNTL_RTC_CLK_CONF, CK8M_DIV_SEL, 12, 3)
    FIELD(RTC_CNTL_RTC_CLK_CONF, DIG_CLK8M_EN, 10, 1)
    FIELD(RTC_CNTL_RTC_CLK_CONF, DIG_CLK8M_D256_EN, 9, 1)
    FIELD(RTC_CNTL_RTC_CLK_CONF, DIG_XTAL32K_EN, 8, 1)
    FIELD(RTC_CNTL_RTC_CLK_CONF, ENB_CK8M_DIV, 7, 1)
    FIELD(RTC_CNTL_RTC_CLK_CONF, ENB_CK8M, 6, 1)
    FIELD(RTC_CNTL_RTC_CLK_CONF, CK8M_DIV, 4, 2)
    FIELD(RTC_CNTL_RTC_CLK_CONF, CK8M_DIV_SEL_VLD, 3, 1)
    FIELD(RTC_CNTL_RTC_CLK_CONF, EFUSE_CLK_FORCE_NOGATING, 2, 1)
    FIELD(RTC_CNTL_RTC_CLK_CONF, EFUSE_CLK_FORCE_GATING, 1, 1)

REG32(RTC_CNTL_RTC_SLOW_CLK_CONF, 0x0074)
    FIELD(RTC_CNTL_RTC_SLOW_CLK_CONF, RTC_SLOW_CLK_NEXT_EDGE, 31, 1)
    FIELD(RTC_CNTL_RTC_SLOW_CLK_CONF, RTC_ANA_CLK_DIV, 23, 8)
    FIELD(RTC_CNTL_RTC_SLOW_CLK_CONF, RTC_ANA_CLK_DIV_VLD, 22, 1)

REG32(RTC_CNTL_RTC_SDIO_CONF, 0x0078)

REG32(RTC_CNTL_RTC_BIAS_CONF, 0x007C)

REG32(RTC_CNTL_RTC, 0x0080)
    FIELD(RTC_CNTL_RTC, RTC_REGULATOR_FORCE_PU, 31, 1)
    FIELD(RTC_CNTL_RTC, RTC_REGULATOR_FORCE_PD, 30, 1)
    FIELD(RTC_CNTL_RTC, RTC_DBOOST_FORCE_PU, 29, 1)
    FIELD(RTC_CNTL_RTC, RTC_DBOOST_FORCE_PD, 28, 1)
    FIELD(RTC_CNTL_RTC, SCK_DCAP, 14, 8)
    FIELD(RTC_CNTL_RTC, DIG_REG_CAL_EN, 7, 1)

REG32(RTC_CNTL_RTC_PWC, 0x0084)
    FIELD(RTC_CNTL_RTC_PWC, RTC_PAD_FORCE_HOLD, 21, 1)

REG32(RTC_CNTL_DIG_PWC, 0x0088)
    FIELD(RTC_CNTL_DIG_PWC, DG_WRAP_PD_EN, 31, 1)
    FIELD(RTC_CNTL_DIG_PWC, WIFI_PD_EN, 30, 1)
    FIELD(RTC_CNTL_DIG_PWC, CPU_TOP_PD_EN, 29, 1)
    FIELD(RTC_CNTL_DIG_PWC, DG_PERI_PD_EN, 28, 1)
    FIELD(RTC_CNTL_DIG_PWC, BT_PD_EN, 27, 1)
    FIELD(RTC_CNTL_DIG_PWC, CPU_TOP_FORCE_PU, 22, 1)
    FIELD(RTC_CNTL_DIG_PWC, CPU_TOP_FORCE_PD, 21, 1)
    FIELD(RTC_CNTL_DIG_PWC, DG_WRAP_FORCE_PU, 20, 1)
    FIELD(RTC_CNTL_DIG_PWC, DG_WRAP_FORCE_PD, 19, 1)
    FIELD(RTC_CNTL_DIG_PWC, WIFI_FORCE_PU, 18, 1)
    FIELD(RTC_CNTL_DIG_PWC, WIFI_FORCE_PD, 17, 1)
    FIELD(RTC_CNTL_DIG_PWC, RTC_FASTMEM_FORCE_LPU, 16, 1)
    FIELD(RTC_CNTL_DIG_PWC, RTC_FASTMEM_FORCE_LPD, 15, 1)
    FIELD(RTC_CNTL_DIG_PWC, DG_PERI_FORCE_PU, 14, 1)
    FIELD(RTC_CNTL_DIG_PWC, DG_PERI_FORCE_PD, 13, 1)
    FIELD(RTC_CNTL_DIG_PWC, BT_FORCE_PU, 12, 1)
    FIELD(RTC_CNTL_DIG_PWC, BT_FORCE_PD, 11, 1)
    FIELD(RTC_CNTL_DIG_PWC, LSLP_MEM_FORCE_PU, 4, 1)
    FIELD(RTC_CNTL_DIG_PWC, LSLP_MEM_FORCE_PD, 3, 1)
    FIELD(RTC_CNTL_DIG_PWC, VDD_SPI_PWR_FORCE, 2, 1)
    FIELD(RTC_CNTL_DIG_PWC, VDD_SPI_PWR_DRV, 0, 2)

REG32(RTC_CNTL_DIG_ISO, 0x008C)
    FIELD(RTC_CNTL_DIG_ISO, DG_WRAP_FORCE_NOISO, 31, 1)
    FIELD(RTC_CNTL_DIG_ISO, DG_WRAP_FORCE_ISO, 30, 1)
    FIELD(RTC_CNTL_DIG_ISO, WIFI_FORCE_NOISO, 29, 1)
    FIELD(RTC_CNTL_DIG_ISO, WIFI_FORCE_ISO, 28, 1)
    FIELD(RTC_CNTL_DIG_ISO, CPU_TOP_FORCE_NOISO, 27, 1)
    FIELD(RTC_CNTL_DIG_ISO, CPU_TOP_FORCE_ISO, 26, 1)
    FIELD(RTC_CNTL_DIG_ISO, DG_PERI_FORCE_NOISO, 25, 1)
    FIELD(RTC_CNTL_DIG_ISO, DG_PERI_FORCE_ISO, 24, 1)
    FIELD(RTC_CNTL_DIG_ISO, BT_FORCE_NOISO, 23, 1)
    FIELD(RTC_CNTL_DIG_ISO, BT_FORCE_ISO, 22, 1)
    FIELD(RTC_CNTL_DIG_ISO, DG_PAD_FORCE_HOLD, 15, 1)
    FIELD(RTC_CNTL_DIG_ISO, DG_PAD_FORCE_UNHOLD, 14, 1)
    FIELD(RTC_CNTL_DIG_ISO, DG_PAD_FORCE_ISO, 13, 1)
    FIELD(RTC_CNTL_DIG_ISO, DG_PAD_FORCE_NOISO, 12, 1)
    FIELD(RTC_CNTL_DIG_ISO, DG_PAD_AUTOHOLD_EN, 11, 1)
    FIELD(RTC_CNTL_DIG_ISO, CLR_DG_PAD_AUTOHOLD, 10, 1)
    FIELD(RTC_CNTL_DIG_ISO, DG_PAD_AUTOHOLD, 9, 1)

REG32(RTC_CNTL_RTC_WDTCONFIG0, 0x0090)
    FIELD(RTC_CNTL_RTC_WDTCONFIG0, WDT_EN, 31, 1)
    FIELD(RTC_CNTL_RTC_WDTCONFIG0, WDT_STG0, 28, 3)
    FIELD(RTC_CNTL_RTC_WDTCONFIG0, WDT_STG1, 25, 3)
    FIELD(RTC_CNTL_RTC_WDTCONFIG0, WDT_STG2, 22, 3)
    FIELD(RTC_CNTL_RTC_WDTCONFIG0, WDT_STG3, 19, 3)
    FIELD(RTC_CNTL_RTC_WDTCONFIG0, WDT_CPU_RESET_LENGTH, 16, 3)
    FIELD(RTC_CNTL_RTC_WDTCONFIG0, WDT_SYS_RESET_LENGTH, 13, 3)
    FIELD(RTC_CNTL_RTC_WDTCONFIG0, WDT_FLASHBOOT_MOD_EN, 12, 1)
    FIELD(RTC_CNTL_RTC_WDTCONFIG0, WDT_PROCPU_RESET_EN, 11, 1)
    FIELD(RTC_CNTL_RTC_WDTCONFIG0, WDT_APPCPU_RESET_EN, 10, 1)
    FIELD(RTC_CNTL_RTC_WDTCONFIG0, WDT_PAUSE_IN_SLP, 9, 1)

REG32(RTC_CNTL_RTC_WDTCONFIG1, 0x0094)
    FIELD(RTC_CNTL_RTC_WDTCONFIG1, WDT_STG0_HOLD, 0, 32)

REG32(RTC_CNTL_RTC_WDTCONFIG2, 0x0098)
    FIELD(RTC_CNTL_RTC_WDTCONFIG2, WDT_STG1_HOLD, 0, 32)

REG32(RTC_CNTL_RTC_WDTCONFIG3, 0x009C)
    FIELD(RTC_CNTL_RTC_WDTCONFIG3, WDT_STG2_HOLD, 0, 32)

REG32(RTC_CNTL_RTC_WDTCONFIG4, 0x00A0)
    FIELD(RTC_CNTL_RTC_WDTCONFIG4, WDT_STG3_HOLD, 0, 32)

REG32(RTC_CNTL_RTC_WDTFEED, 0x00A4)
    FIELD(RTC_CNTL_RTC_WDTFEED, RTC_WDT_FEED, 31, 1)

REG32(RTC_CNTL_RTC_WDTWPROTECT, 0x00A8)
    FIELD(RTC_CNTL_RTC_WDTWPROTECT, WDT_WKEY, 0, 32)

REG32(RTC_CNTL_RTC_SWD_CONF, 0x00AC)
    FIELD(RTC_CNTL_RTC_SWD_CONF, SWD_AUTO_FEED_EN, 31, 1)
    FIELD(RTC_CNTL_RTC_SWD_CONF, SWD_DISABLE, 30, 1)
    FIELD(RTC_CNTL_RTC_SWD_CONF, SWD_FEED, 29, 1)
    FIELD(RTC_CNTL_RTC_SWD_CONF, SWD_RST_FLAG_CLR, 28, 1)
    FIELD(RTC_CNTL_RTC_SWD_CONF, SWD_SIGNAL_WIDTH, 18, 10)
    FIELD(RTC_CNTL_RTC_SWD_CONF, SWD_BYPASS_RST, 17, 1)
    FIELD(RTC_CNTL_RTC_SWD_CONF, SWD_FEED_INT, 1, 1)
    FIELD(RTC_CNTL_RTC_SWD_CONF, SWD_RESET_FLAG, 0, 1)

REG32(RTC_CNTL_RTC_SWD_WPROTECT, 0x00B0)
    FIELD(RTC_CNTL_RTC_SWD_WPROTECT, SWD_WKEY, 0, 32)

REG32(RTC_CNTL_RTC_SW_CPU_STALL, 0x00B4)
    FIELD(RTC_CNTL_RTC_SW_CPU_STALL, SW_STALL_PROCPU_C1, 26, 6)
    FIELD(RTC_CNTL_RTC_SW_CPU_STALL, SW_STALL_APPCPU_C1, 20, 6)

REG32(RTC_CNTL_RTC_STORE4, 0x00B8)
    FIELD(RTC_CNTL_RTC_STORE4, RTC_SCRATCH4, 0, 32)

REG32(RTC_CNTL_RTC_STORE5, 0x00BC)
    FIELD(RTC_CNTL_RTC_STORE5, RTC_SCRATCH5, 0, 32)

REG32(RTC_CNTL_RTC_STORE6, 0x00C0)
    FIELD(RTC_CNTL_RTC_STORE6, RTC_SCRATCH6, 0, 32)

REG32(RTC_CNTL_RTC_STORE7, 0x00C4)
    FIELD(RTC_CNTL_RTC_STORE7, RTC_SCRATCH7, 0, 32)

REG32(RTC_CNTL_RTC_LOW_POWER_ST, 0x00C8)
    FIELD(RTC_CNTL_RTC_LOW_POWER_ST, RTC_RDY_FOR_WAKEUP, 19, 1)

REG32(RTC_CNTL_RTC_DIAG0, 0x00CC)

REG32(RTC_CNTL_RTC_PAD_HOLD, 0x00D0)
    FIELD(RTC_CNTL_RTC_PAD_HOLD, RTC_GPIO_PIN5_HOLD, 5, 1)
    FIELD(RTC_CNTL_RTC_PAD_HOLD, RTC_GPIO_PIN4_HOLD, 4, 1)
    FIELD(RTC_CNTL_RTC_PAD_HOLD, RTC_GPIO_PIN3_HOLD, 3, 1)
    FIELD(RTC_CNTL_RTC_PAD_HOLD, RTC_GPIO_PIN2_HOLD, 2, 1)
    FIELD(RTC_CNTL_RTC_PAD_HOLD, RTC_GPIO_PIN1_HOLD, 1, 1)
    FIELD(RTC_CNTL_RTC_PAD_HOLD, RTC_GPIO_PIN0_HOLD, 0, 1)

REG32(RTC_CNTL_DIG_PAD_HOLD, 0x00D4)
    FIELD(RTC_CNTL_DIG_PAD_HOLD, DIG_PAD_HOLD, 0, 32)

REG32(RTC_CNTL_RTC_BROWN_OUT, 0x00D8)
    FIELD(RTC_CNTL_RTC_BROWN_OUT, RTC_BROWN_OUT_DET, 31, 1)
    FIELD(RTC_CNTL_RTC_BROWN_OUT, BROWN_OUT_ENA, 30, 1)
    FIELD(RTC_CNTL_RTC_BROWN_OUT, BROWN_OUT_CNT_CLR, 29, 1)
    FIELD(RTC_CNTL_RTC_BROWN_OUT, BROWN_OUT_ANA_RST_EN, 28, 1)
    FIELD(RTC_CNTL_RTC_BROWN_OUT, BROWN_OUT_RST_SEL, 27, 1)
    FIELD(RTC_CNTL_RTC_BROWN_OUT, BROWN_OUT_RST_ENA, 26, 1)
    FIELD(RTC_CNTL_RTC_BROWN_OUT, BROWN_OUT_RST_WAIT, 16, 10)
    FIELD(RTC_CNTL_RTC_BROWN_OUT, BROWN_OUT_PD_RF_ENA, 15, 1)
    FIELD(RTC_CNTL_RTC_BROWN_OUT, BROWN_OUT_CLOSE_FLASH_ENA, 14, 1)

REG32(RTC_CNTL_RTC_TIME_LOW1, 0x00DC)
    FIELD(RTC_CNTL_RTC_TIME_LOW1, RTC_TIMER_VALUE1_LOW, 0, 32)

REG32(RTC_CNTL_RTC_TIME_HIGH1, 0x00E0)
    FIELD(RTC_CNTL_RTC_TIME_HIGH1, RTC_TIMER_VALUE1_HIGH, 0, 16)

REG32(RTC_CNTL_RTC_XTAL32K_CLK_FACTOR, 0x00E4)
    FIELD(RTC_CNTL_RTC_XTAL32K_CLK_FACTOR, XTAL32K_CLK_FACTOR, 0, 32)

REG32(RTC_CNTL_RTC_XTAL32K_CONF, 0x00E8)
    FIELD(RTC_CNTL_RTC_XTAL32K_CONF, XTAL32K_STABLE_THRES, 28, 4)
    FIELD(RTC_CNTL_RTC_XTAL32K_CONF, XTAL32K_WDT_TIMEOUT, 20, 8)
    FIELD(RTC_CNTL_RTC_XTAL32K_CONF, XTAL32K_RESTART_WAIT, 4, 16)
    FIELD(RTC_CNTL_RTC_XTAL32K_CONF, XTAL32K_RETURN_WAIT, 0, 4)

REG32(RTC_CNTL_RTC_USB_CONF, 0x00EC)
    FIELD(RTC_CNTL_RTC_USB_CONF, IO_MUX_RESET_DISABLE, 18, 1)

REG32(RTC_CNTL_RTC_SLP_REJECT_CAUSE, 0x00F0)
    FIELD(RTC_CNTL_RTC_SLP_REJECT_CAUSE, REJECT_CAUSE, 0, 18)

REG32(RTC_CNTL_RTC_OPTION1, 0x00F4)
    FIELD(RTC_CNTL_RTC_OPTION1, FORCE_DOWNLOAD_BOOT, 0, 1)

REG32(RTC_CNTL_RTC_SLP_WAKEUP_CAUSE, 0x00F8)
    FIELD(RTC_CNTL_RTC_SLP_WAKEUP_CAUSE, WAKEUP_CAUSE, 0, 17)

REG32(RTC_CNTL_RTC_ULP_CP_TIMER_1, 0x00FC)
    FIELD(RTC_CNTL_RTC_ULP_CP_TIMER_1, ULP_CP_TIMER_SLP_CYCLE, 8, 24)

REG32(RTC_CNTL_INT_ENA_RTC_W1TS, 0x0100)
    FIELD(RTC_CNTL_INT_ENA_RTC_W1TS, RTC_BBPLL_CAL_INT_ENA_W1TS, 20, 1)
    FIELD(RTC_CNTL_INT_ENA_RTC_W1TS, RTC_GLITCH_DET_INT_ENA_W1TS, 19, 1)
    FIELD(RTC_CNTL_INT_ENA_RTC_W1TS, RTC_XTAL32K_DEAD_INT_ENA_W1TS, 16, 1)
    FIELD(RTC_CNTL_INT_ENA_RTC_W1TS, RTC_SWD_INT_ENA_W1TS, 15, 1)
    FIELD(RTC_CNTL_INT_ENA_RTC_W1TS, RTC_MAIN_TIMER_INT_ENA_W1TS, 10, 1)
    FIELD(RTC_CNTL_INT_ENA_RTC_W1TS, RTC_BROWN_OUT_INT_ENA_W1TS, 9, 1)
    FIELD(RTC_CNTL_INT_ENA_RTC_W1TS, RTC_WDT_INT_ENA_W1TS, 3, 1)
    FIELD(RTC_CNTL_INT_ENA_RTC_W1TS, SLP_REJECT_INT_ENA_W1TS, 1, 1)
    FIELD(RTC_CNTL_INT_ENA_RTC_W1TS, SLP_WAKEUP_INT_ENA_W1TS, 0, 1)

REG32(RTC_CNTL_INT_ENA_RTC_W1TC, 0x0104)
    FIELD(RTC_CNTL_INT_ENA_RTC_W1TC, RTC_BBPLL_CAL_INT_ENA_W1TC, 20, 1)
    FIELD(RTC_CNTL_INT_ENA_RTC_W1TC, RTC_GLITCH_DET_INT_ENA_W1TC, 19, 1)
    FIELD(RTC_CNTL_INT_ENA_RTC_W1TC, RTC_XTAL32K_DEAD_INT_ENA_W1TC, 16, 1)
    FIELD(RTC_CNTL_INT_ENA_RTC_W1TC, RTC_SWD_INT_ENA_W1TC, 15, 1)
    FIELD(RTC_CNTL_INT_ENA_RTC_W1TC, RTC_MAIN_TIMER_INT_ENA_W1TC, 10, 1)
    FIELD(RTC_CNTL_INT_ENA_RTC_W1TC, RTC_BROWN_OUT_INT_ENA_W1TC, 9, 1)
    FIELD(RTC_CNTL_INT_ENA_RTC_W1TC, RTC_WDT_INT_ENA_W1TC, 3, 1)
    FIELD(RTC_CNTL_INT_ENA_RTC_W1TC, SLP_REJECT_INT_ENA_W1TC, 1, 1)
    FIELD(RTC_CNTL_INT_ENA_RTC_W1TC, SLP_WAKEUP_INT_ENA_W1TC, 0, 1)

REG32(RTC_CNTL_RTC_CNTL_RETENTION_CTRL, 0x0108)
    FIELD(RTC_CNTL_RTC_CNTL_RETENTION_CTRL, RETENTION_WAIT, 27, 5)
    FIELD(RTC_CNTL_RTC_CNTL_RETENTION_CTRL, RETENTION_EN, 26, 1)
    FIELD(RTC_CNTL_RTC_CNTL_RETENTION_CTRL, RETENTION_CLKOFF_WAIT, 22, 4)
    FIELD(RTC_CNTL_RTC_CNTL_RETENTION_CTRL, RETENTION_DONE_WAIT, 19, 3)
    FIELD(RTC_CNTL_RTC_CNTL_RETENTION_CTRL, RETENTION_CLK_SEL, 18, 1)

REG32(RTC_CNTL_RTC_FIB_SEL, 0x010C)
    FIELD(RTC_CNTL_RTC_FIB_SEL, RTC_FIB_SEL, 0, 3)

REG32(RTC_CNTL_RTC_CNTL_GPIO_WAKEUP, 0x0110)
    FIELD(RTC_CNTL_RTC_CNTL_GPIO_WAKEUP, RTC_GPIO_PIN0_WAKEUP_ENABLE, 31, 1)
    FIELD(RTC_CNTL_RTC_CNTL_GPIO_WAKEUP, RTC_GPIO_PIN1_WAKEUP_ENABLE, 30, 1)
    FIELD(RTC_CNTL_RTC_CNTL_GPIO_WAKEUP, RTC_GPIO_PIN2_WAKEUP_ENABLE, 29, 1)
    FIELD(RTC_CNTL_RTC_CNTL_GPIO_WAKEUP, RTC_GPIO_PIN3_WAKEUP_ENABLE, 28, 1)
    FIELD(RTC_CNTL_RTC_CNTL_GPIO_WAKEUP, RTC_GPIO_PIN4_WAKEUP_ENABLE, 27, 1)
    FIELD(RTC_CNTL_RTC_CNTL_GPIO_WAKEUP, RTC_GPIO_PIN5_WAKEUP_ENABLE, 26, 1)
    FIELD(RTC_CNTL_RTC_CNTL_GPIO_WAKEUP, RTC_GPIO_PIN0_INT_TYPE, 23, 3)
    FIELD(RTC_CNTL_RTC_CNTL_GPIO_WAKEUP, RTC_GPIO_PIN1_INT_TYPE, 20, 3)
    FIELD(RTC_CNTL_RTC_CNTL_GPIO_WAKEUP, RTC_GPIO_PIN2_INT_TYPE, 17, 3)
    FIELD(RTC_CNTL_RTC_CNTL_GPIO_WAKEUP, RTC_GPIO_PIN3_INT_TYPE, 14, 3)
    FIELD(RTC_CNTL_RTC_CNTL_GPIO_WAKEUP, RTC_GPIO_PIN4_INT_TYPE, 11, 3)
    FIELD(RTC_CNTL_RTC_CNTL_GPIO_WAKEUP, RTC_GPIO_PIN5_INT_TYPE, 8, 3)
    FIELD(RTC_CNTL_RTC_CNTL_GPIO_WAKEUP, RTC_GPIO_PIN_CLK_GATE, 7, 1)
    FIELD(RTC_CNTL_RTC_CNTL_GPIO_WAKEUP, RTC_GPIO_WAKEUP_STATUS_CLR, 6, 1)
    FIELD(RTC_CNTL_RTC_CNTL_GPIO_WAKEUP, RTC_GPIO_WAKEUP_STATUS, 0, 6)

REG32(RTC_CNTL_RTC_CNTL_DBG_SEL, 0x0114)

REG32(RTC_CNTL_RTC_CNTL_DBG_MAP, 0x0118)

REG32(RTC_CNTL_RTC_CNTL_SENSOR_CTRL, 0x011C)
    FIELD(RTC_CNTL_RTC_CNTL_SENSOR_CTRL, FORCE_XPD_SAR, 30, 2)
    FIELD(RTC_CNTL_RTC_CNTL_SENSOR_CTRL, SAR2_PWDET_CCT, 27, 3)

REG32(RTC_CNTL_RTC_CNTL_DBG_SAR_SEL, 0x0120)
    FIELD(RTC_CNTL_RTC_CNTL_DBG_SAR_SEL, SAR_DEBUG_SEL, 27, 5)

REG32(RTC_CNTL_RTC_CNTL_PG_CTRL, 0x0124)
    FIELD(RTC_CNTL_RTC_CNTL_PG_CTRL, POWER_GLITCH_EN, 31, 1)
    FIELD(RTC_CNTL_RTC_CNTL_PG_CTRL, POWER_GLITCH_EFUSE_SEL, 30, 1)
    FIELD(RTC_CNTL_RTC_CNTL_PG_CTRL, POWER_GLITCH_FORCE_PU, 29, 1)
    FIELD(RTC_CNTL_RTC_CNTL_PG_CTRL, POWER_GLITCH_FORCE_PD, 28, 1)
    FIELD(RTC_CNTL_RTC_CNTL_PG_CTRL, POWER_GLITCH_DSENSE, 26, 2)

REG32(RTC_CNTL_DATE, 0x01fc)
